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VHDL Programming Training for FPGA in Singapore - VDHL Programming, FPGA Architecture,

Course Information

  • Sessions 2 days
  • Duration 15 hrs
  • Level Intermediate
  • Assessment NA

Venue

12 Woodlands Square #07-85/86/87 Woods Square Tower 1, Singapore 737715. 5 mins walk from Woodlands (NS9) MRT station.

The venue is disabled-friendly.

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Certification

  • Certificate of Completion from Tertiary Courses - Upon meeting at least 75% attendance and passing the assessment(s), participants will receive a Certificate of Completion from Tertiary Courses.

VHDL Programming Training for FPGA

Course Code: C419

1 Review(s) | Add Your Review

What's This Course About

The VHDL Programming Training for FPGA, meticulously structured for professionals and enthusiasts eager to harness the full potential of FPGA design. This course offers a detailed insight into VHDL syntax and coding styles pivotal to logic design, coupled with hands-on sessions on writing robust VHDL RTL hardware designs. By incorporating good coding practices, learners will comprehend the synthesizable subset of VHDL, shedding light on potential pitfalls and problematic coding areas.

Furthermore, participants will explore the dynamic world of standard VHDL packages, including std_logic_1164 and numeric_std, mastering types, overloading, and conversion functions. The training doesn't stop at the basics; delve into advanced testbench writing using TEXTIO, and craft transaction-based testbenches through subprograms. By the course's conclusion, attendees will be adept at leveraging VHDL simulation and synthesis tools, ensuring an elevated competency in FPGA design and VHDL programming.

Funding Options

No funding is available for this course

Course Fee

$600.00 (GST-exclusive)
$654.00 (GST-inclusive)

Course Date

Course Time

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Additional Note

Please bring your own laptop for hands-on training. If you don't have laptop, we can provide spare laptop for training use.

Post-Course Support

  • We provide free consultation related to the subject matter after the course.
  • Please email your queries to enquiry@tertiaryinfotech.com and we will forward your queries to the subject matter experts.

Cancellation & Reschedule Policy

  • You can register your interest without upfront payment. There is no penalty for withdrawal of the course before the class commences.
  • We reserve the right to cancel or re-schedule the course due to unforeseen circumstances. If the course is cancelled, we will refund 100% for any paid amount.
  • Note the venue of the training is subject to changes due to availability of the classroom.

Course Details

Course Details

What You'll Learn

FPGA Design FLOW

Motivation

Topic 1 : Introduction to VHDL

Library & Packages

Entity/Modes

Architecture

Topic 2: VHDL Data Types

Language Elements

Identifiers

Literals

Types

Conversion (Advance)

Object Types

TEXTIO

Topic 3: Operators

Logical Operator

Relational Operators

Arithmetic Operator

Resize function

Shift Operators

Multiplying Operators

Miscellaneous Operators

Topic 4: Concurrent Statements

Aggregates

Drivers

Concurrent Statement

Component Instantiation

Block Statement

Generate Statement

Topic 5: Sequential Statements

Process statement / Sensitivity List

Wait statement

IF statement

Case statement

Loop

Define Range

Variables

Variables Vs Signals

Topic 6: Configuration

Generic

Operator Overloading

Attributes

Topic 7: Lab Exercise

Combinational Logic

Topic 8: State Machine

Mealy

Moore

Topic 9: Simulation

Steps of simulation / Simulation Deltas

Inertia Delay / Transport delay

Test bench

Topic 10: Lab Activities

Design Entry

Writing VHDL code

Test bench

Simulating VHDL code with Vivado (Xilinx)

Synthesize the code

Course Info

Promotion Code

Your will get 10% discount voucher for 2nd course onwards if you write us a Google review.

Minimum Entry Requirement

Knowledge and Skills

  • Able to operate using computer functions
  • Minimum 3 GCE ‘O’ Levels Passes including English or WPL Level 5 (Average of Reading, Listening, Speaking & Writing Scores)

Attitude

  • Positive Learning Attitude
  • Enthusiastic Learner

Experience

  • Minimum of 1 year of working experience.

Target Age Group: 18-65 years old

Minimum Software/Hardware Requirement

Software:

TBD

Hardware: Window or Mac Laptops

Job Roles

Job Roles

  • Digital IC Designers
  • VHDL/VERILOG Programmers
  • FPGA Architects
  • Embedded Design Engineers

Trainers

Trainers

Sim Cher Khern

Sim Cher Khern (Sim CK) has over 20 years of working experience in a number of product development lifecycles, involving embedded firmware and FPGA programming, as well as high speed embedded system hardware design and PCB layout, where EMI/EMC considerations are critical for product delivery. He has also gained much project management experience and knowledge working with various operating systems (Windows, Linux, RTOS), networking technologies and web interface while developing the products.

Being a technology enthusiast, he keeps up with emerging technologies and likes to get his hands dirty with projects. In the process, he has picked up knowledge in full stack web development and its deployment to the cloud platform. He has also acquired knowledge on Cybersecurity threats, Network Defense and Ethical Hacking.

CK holds a MSc in Embedded Systems from Nanyang Technological University (NTU), as well as Cybersecurity certifications from EC-Council (ECSS, CND, CEH and CHFI).

His current area of interests include Cybersecurity, Embedded system hardware and firmware, IoT, Web technologies and Machine learning. They are intertwined in today’s business systems setup.

Review

Customer Reviews (1)

Will Recommend Review by Course Participant/Trainee
1. Do you find the course meet your expectation?
2. Do you find the trainer knowledgeable in this subject?
3. How do you find the training environment
Would be good if there is FPGA hardware included with the course, I had to buy my own hardware just to appreciate and be able to practice what i have learnt from this course. Course fees will be more expensive but it would be good (Posted on 11/4/2019)

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