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VHDL Programming Training for FPGA

HDL (Hardware Descriptive Language) based design has established itself as the modern approach to design of digital systems, with VHDL (VHSIC Hardware Description Language) and Verilog HDL being the two dominant HDLs. This course is a thorough introduction to the VHDL programming language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered.

Course Objectives
Upon completion of this course, students will be able to:

  • • Understand VHDL syntax and coding styles relevant to logic design. 
  • • Write VHDL RTL hardware designs using good coding practices. 
  • • Understand the synthesizable subset of VHDL. 
  • • Understand problematic issues in coding hardware. 
  • • Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164 and numeric_std). 
  • • Print messages in testbenches using TEXTIO. 
  • • Write simple transaction-based testbenches using subprograms.
  • • Use your VHDL simulation and synthesis tools.


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Course Code: CRS-N-0040114

Course Booking

$498.00

Course Cancellation/Reschedule Policy

We reserve the right to cancel or re-schedule the course due to unforeseen circumstances. If the course is cancelled, we will refund 100% to participants.
Note the venue of the training is subject to changes due to class size and availability of the classroom.
Note the minimal class size to start a class is 3 Pax.

Course Details

Day 1

Module 1 : VHDL Code Structure

  • Entity
  • Architecture
  • Library

Module 2: VHDL Data Types

  • Standard data types
  • Datatype 'time'
  • Definitions of Arrays
  • Integer and bit type
  • Assignment and Array types
  • Type of Assignment for 'bit' Data types
  • Aggregates
  • Slice of Array
  • Concatenations 

Module 3: Operators

  • Logical Operator
  • Logical Operator with Arrays
  • Arithmetic Operator
  • Relation Operators
  • Shift Operators
  • Comparison Operation with Arrays

 Day 2

Module 4: Sequential Statement

  • IF Statement
  • Case Statement
  • Define Range
  • For Loop
  • Wait Statements
  • Variables                   
  • Variables Vs Signals
  • Global Variables  

 Module 5 : Statemachine

  • Testbench
  • TextIO

Module 6:  Lab activities

  • Installing Software
  • Simulation VHDL code with Modelsim

Who Should Attend

  • Digital IC Designers
  • VHDL/VERILOG Programmers
  • FPGA Architects
  • Embedded Design Engineers

Prerequisite

Nil

Trainers

FPGA TrainerGaurav Rastogi is an experienced electronics FPGA design Engineer. He has more than 15 years’ experience in the FPGA industry and worked in a number of MNCs He has a lot of experience in System Design using FPGA and expertise in VHDL/Verilog programming, C, Perl, Python, Matlab, Simulink

He holds Bachelor of Electronics, Post-Graduation Diploma in VLSI design and Specialist Diploma in IoT Design.

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