FPGA Designer Training

Day 1

Topic 1: Introduction to FPGA

• Cyclone/Stratix device Architecture
• Introduction to Quartus II
• Creating Project 
• Using Editor & Design Entry

Topic 2: Analysis and Elaboration

• I/O Assignment
• Configure voltage for I/0
• I/O Assignment Analysis
• Synthesis
• Netlist Viewer

Topic 3: Constraints

• Importance of Constraints in Design 
• Clock frequency
• Asynchronous & Synchronous Design
• False Path/Multicycle path

Day 2

Topic 4: Debugging Tools

• Power Analysis 
• SignalTap II embedded logic analyzer
• JTAG Chain Debug Tool
• In-System Memory Content Editor

Topic 5: Placing Design in FPGA

• Fitter (Place & Route)
• Chip Planner
• Assembler (Generating Programming file)
• Downloading Design in FPGA

Topic 6: Static Time analysis (STA)

• Running TimeQuest Timing Analyzer
• Understanding reports 
• Understand setup/hold violation & failing paths
• Constraining and understanding TCL Commands

Promotion Code

Your will get 10% discount voucher for 2nd course onwards if you write us a Google review.

Minimum Entry Requirement

Knowledge and Skills

• Able to operate using computer functions
• Minimum 3 GCE ‘O’ Levels Passes including English or WPL Level 5 (Average of Reading, Listening, Speaking & Writing Scores)

Attitude

• Positive Learning Attitude
• Enthusiastic Learner

Experience

• Minimum of 1 year of working experience.

Target Age Group: 18-65 years old

Minimum Software/Hardware Requirement

Software:

TBD

Hardware: Window or Mac Laptops

• Digital IC Aesigners
• VHDL/VERILOG Arogrammers
• FPGA Architects
• Embedded design Engineers

Sim Cher Khern (Sim CK) has over 20 years of working experience in a number of product development lifecycles, involving embedded firmware and FPGA programming, as well as high speed embedded system hardware design and PCB layout, where EMI/EMC considerations are critical for product delivery. He has also gained much project management experience and knowledge working with various operating systems (Windows, Linux, RTOS), networking technologies and web interface while developing the products.

Being a technology enthusiast, he keeps up with emerging technologies and likes to get his hands dirty with projects. In the process, he has picked up knowledge in full stack web development and its deployment to the cloud platform. He has also acquired knowledge on Cybersecurity threats, Network Defense and Ethical Hacking.

CK holds a MSc in Embedded Systems from Nanyang Technological University (NTU), as well as Cybersecurity certifications from EC-Council (ECSS, CND, CEH and CHFI).

His current area of interests include Cybersecurity, Embedded system hardware and firmware, IoT, Web technologies and Machine learning. They are intertwined in today’s business systems setup.

Daniel Kho spent most of his more than 14 years of experience working on digital IP design and test. Throughout his career, he has designed and veried safety- and mission-critical digi- tal signal processing (DSP) and reduced-instruction-set computer (RISC) processor subsystems, for companies such as Altera, Motorola, and ASML BV (Netherlands). He has extensive experience designing complex SoC subsystems and bus interfaces, and pioneered hardware-based transaction-level modelling. He is experienced in both FPGA and ASIC design.

Daniel is a registered Certified Professional Trainer and a Certified International Professional Manager of the IPMA, United Kingdom. Prior to joining an integrated circuit (IC) design company in Singapore, he served as the principal engineer for a company he founded, Tauhop Solutions. During his spare time, he does consulting work and conducts trainings in the area of digital design and simulations, SoC bus architecture design, and DSP. He enjoys sharing his experience in making complex designs and testbenches easy and fun. He has also contributed to the IEEE P1076-2008 VHDL standard, and continues working towards advancing the microelectronics industry. He has served as a reviewer for several international journals and conferences. Daniel is a Senior Member of the IEEE