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Verilog Programming Training for FPGA in Singapore

Course Information

  • Sessions 2 days
  • Duration 15 hrs
  • Level Intermediate
  • Assessment NA

Venue

12 Woodlands Square #07-85/86/87 Woods Square Tower 1, Singapore 737715. 5 mins walk from Woodlands (NS9) MRT station.

The venue is disabled-friendly.

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Certification

  • Certificate of Completion from Tertiary Infotech - Upon meeting at least 75% attendance and passing the assessment(s), participants will receive a Certificate of Completion from Tertiary Infotech.

Verilog Programming Training for FPGA

Course Code: C420

1 Review(s) | Add Your Review

What's This Course About

A meticulously crafted Verilog Programming Training for FPGA enthusiasts and professionals, positioning them at the forefront of modern logic design. Participants will gain a profound understanding of VERILOG syntax and the pivotal coding styles that resonate with efficient logic design. The training emphasizes writing VERILOG RTL hardware designs with a keen focus on best coding practices, ensuring robust and optimized outcomes.

Navigating deeper, learners will be enlightened on the synthesizable subset of VERILOG, coupled with the know-how of addressing problematic coding issues in hardware. The course curriculum further integrates essential skills like printing messages in testbenches and scripting transaction-based testbenches using subprograms. With hands-on guidance on leveraging VERILOG simulation and synthesis tools, participants will be fully equipped to pioneer innovative FPGA solutions and drive excellence in their respective domains.

Funding Options

No funding is available for this course

Course Fee

$600.00 (GST-exclusive)
$654.00 (GST-inclusive)

Course Date

Course Time

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Additional Note

Please bring your own laptop for hands-on training. If you don't have laptop, we can provide spare laptop for training use.

Post-Course Support

  • We provide free consultation related to the subject matter after the course.
  • Please email your queries to enquiry@tertiaryinfotech.com and we will forward your queries to the subject matter experts.

Cancellation & Reschedule Policy

  • You can register your interest without upfront payment. There is no penalty for withdrawal of the course before the class commences.
  • We reserve the right to cancel or re-schedule the course due to unforeseen circumstances. If the course is cancelled, we will refund 100% for any paid amount.
  • Note the venue of the training is subject to changes due to availability of the classroom.

Course Details

Course Details

What You'll Learn

FPGA Design FLOW

Motivation

Topic 1 : Architecture of FPGA

Introduction to Programmable logic device (PLD)

Architecture

Structure of PLD

Topic 2 : Introduction to Verilog

Levels of Abstraction

Syntax & Semantics

Reserved Keywords

Topic 3: Verilog Ports

Ports declaration

Data types

Physical

Abstract

Constant

Topic 4: Operators

Arithmetic Operator

Bit Wise

Logical

Reduction

Shift

Relational/Equality/Concatenation/Replication/Conditional

Topic 5: Modeling

Data Flow

Behavioral

Structural

Topic 6: Timing Control

Inertia Delay

Transport Delay

Event Control

Back-Annotation

Topic 7 : Conditional statement

if

Nested if

Case, casex, casez

Topic 8: User Define Primitives.

Process statement / Sensitivity List

Topic 9: Lab Exercise

Combinational Logic

Topic 10: State Machine

Mealy

Moore

Topic 11: Simulation

Steps of simulation / Simulation Deltas

Test bench

Topic 13: Lab Activities

Design Entry

Writing Verilog code

Test bench

Simulating Verilog code with Vivado (Xilinx)

Synthesize the code

Course Info

Promotion Code

Your will get 10% discount voucher for 2nd course onwards if you write us a Google review.

Minimum Entry Requirement

Knowledge and Skills

  • Able to operate using computer functions
  • Minimum 3 GCE ‘O’ Levels Passes including English or WPL Level 5 (Average of Reading, Listening, Speaking & Writing Scores)

Attitude

  • Positive Learning Attitude
  • Enthusiastic Learner

Experience

  • Minimum of 1 year of working experience.

Target Age Group: 18-65 years old

Minimum Software/Hardware Requirement

Software:

Hardware: Window or Mac Laptops

Job Roles

Job Roles

  • Digital IC Designers
  • VHDL/VERILOG Programmers
  • FPGA Architects
  • Embedded Design Engineers

Trainers

Trainers

Dr. Florence Choong

Dr. Florence Choong received the BEng. (First class) from Multimedia University, Malaysia in 2002. She then completed her Masters of Engineering Science (MEngSc) degree in Multimedia University, Cyberjaya in 2005 and Ph.D. in Engineering in 2012. Recently, she has completed her Masters in Business Administration (MBA) from the University of Derby, UK.

Upon graduation, she started her career in the telecommunications and networking industry where she served TM for three years in various departments such as networking, IT, quality assurance and customer service. Being passionate in research and training and educating the youth, she then moved to the academic and research line where she joined Multimedia University (MMU) as a lecturer in 2005. She then moved on to University Tunku Abdul Rahman (UTAR) in 2008 as a senior lecturer. She was the Head of the Electrical and Electronics Engineering department at Taylor’s University leading the program to its first accreditation. At present, she is a senior lecturer and is also very active in research. She has a total of more than 10 years of teaching experience. She is also a Chartered Engineer and is registered with the Board of Engineers Malaysia (BEM) and IEM. She is also the advisor to the Taylors IET On Campus.

She is author and co-author of numerous international journal and conference papers published by renowned journals in power quality, VLSI system design and artificial intelligence. Her current research interests are in the area of artificial intelligence, digital and VLSI design. She has also extended her skills and knowledge in this area through various consultancy works.

Sim Cher Khern

Sim Cher Khern (Sim CK) has over 20 years of working experience in a number of product development lifecycles, involving embedded firmware and FPGA programming, as well as high speed embedded system hardware design and PCB layout, where EMI/EMC considerations are critical for product delivery. He has also gained much project management experience and knowledge working with various operating systems (Windows, Linux, RTOS), networking technologies and web interface while developing the products.

Being a technology enthusiast, he keeps up with emerging technologies and likes to get his hands dirty with projects. In the process, he has picked up knowledge in full stack web development and its deployment to the cloud platform. He has also acquired knowledge on Cybersecurity threats, Network Defense and Ethical Hacking.

CK holds a MSc in Embedded Systems from Nanyang Technological University (NTU), as well as Cybersecurity certifications from EC-Council (ECSS, CND, CEH and CHFI).

His current area of interests include Cybersecurity, Embedded system hardware and firmware, IoT, Web technologies and Machine learning. They are intertwined in today’s business systems setup.

Review

Customer Reviews (1)

will recommend Review by Course Participant/Trainee
1. Do you find the course meet your expectation?
2. Do you find the trainer knowledgeable in this subject?
3. How do you find the training environment
The order of the hands-on training needs rearrangement. The lab order should be from easiest to the most complicated. Our training order is (by Lab #): 1-3-2-4, but in my opinion, a better order is: 1-3-4-2. Lab #2 includes setting up the hardware pin which, understandably, should be placed correctly in 2nd. But the code needed to work on it is the longest, so it might be better to split it into a more simple I/O with hardware assignment as #2. (Posted on 6/4/2021)

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