Verilog Programming Training for FPGA

Day 1

FPGA Design FLOW

• Motivation

Topic 1 : Architecture of FPGA

• Introduction to Programmable logic device (PLD)
• Architecture
• Structure of PLD

Topic 2 : Introduction to Verilog

• Levels of Abstraction
• Syntax & Semantics
• Reserved Keywords

Topic 3: Verilog Ports

• Ports declaration
• Data types
• Physical
• Abstract
• Constant

Topic 4: Operators

• Arithmetic Operator
• Bit Wise
• Logical
• Reduction
• Shift
• Relational/Equality/Concatenation/Replication/Conditional

Topic 5: Modeling

• Data Flow
• Behavioral
• Structural

Topic 6: Timing Control

• Inertia Delay
• Transport Delay
• Event Control
• Back-Annotation

Topic 7 : Conditional statement

• if
• Nested if
• Case, casex, casez

Topic 8: User Define Primitives.

• Process statement / Sensitivity List

Topic 9: Lab Exercise

• Combinational Logic

Day 2

Topic 10: State Machine

• Mealy 
• Moore

Topic 11: Simulation

• Steps of simulation / Simulation Deltas
• Test bench

Topic 13: Lab Activities

• Design Entry
• Writing Verilog code 
• Test bench 
• Simulating Verilog code with Vivado (Xilinx)
• Synthesize the code

Promotion Code

Your will get 10% discount voucher for 2nd course onwards if you write us a Google review.

Minimum Entry Requirement

Knowledge and Skills

• Able to operate using computer functions
• Minimum 3 GCE ‘O’ Levels Passes including English or WPL Level 5 (Average of Reading, Listening, Speaking & Writing Scores)

Attitude

• Positive Learning Attitude
• Enthusiastic Learner

Experience

• Minimum of 1 year of working experience.

Target Age Group: 18-65 years old

Minimum Software/Hardware Requirement

Software:

• Vivado Design Suite https://www.xilinx.com/support/download.html

Hardware: Window or Mac Laptops

• Digital IC Designers
• VHDL/VERILOG Programmers
• FPGA Architects
• Embedded Design Engineers

Sim Cher Khern (Sim CK) has over 20 years of working experience in a number of product development lifecycles, involving embedded firmware and FPGA programming, as well as high speed embedded system hardware design and PCB layout, where EMI/EMC considerations are critical for product delivery. He has also gained much project management experience and knowledge working with various operating systems (Windows, Linux, RTOS), networking technologies and web interface while developing the products.

Being a technology enthusiast, he keeps up with emerging technologies and likes to get his hands dirty with projects. In the process, he has picked up knowledge in full stack web development and its deployment to the cloud platform. He has also acquired knowledge on Cybersecurity threats, Network Defense and Ethical Hacking.

CK holds a MSc in Embedded Systems from Nanyang Technological University (NTU), as well as Cybersecurity certifications from EC-Council (ECSS, CND, CEH and CHFI).

His current area of interests include Cybersecurity, Embedded system hardware and firmware, IoT, Web technologies and Machine learning. They are intertwined in today’s business systems setup.

Daniel Kho spent most of his more than 14 years of experience working on digital IP design and test. Throughout his career, he has designed and veried safety- and mission-critical digi- tal signal processing (DSP) and reduced-instruction-set computer (RISC) processor subsystems, for companies such as Altera, Motorola, and ASML BV (Netherlands). He has extensive experience designing complex SoC subsystems and bus interfaces, and pioneered hardware-based transaction-level modelling. He is experienced in both FPGA and ASIC design.

Daniel is a registered Certified Professional Trainer and a Certified International Professional Manager of the IPMA, United Kingdom. Prior to joining an integrated circuit (IC) design company in Singapore, he served as the principal engineer for a company he founded, Tauhop Solutions. During his spare time, he does consulting work and conducts trainings in the area of digital design and simulations, SoC bus architecture design, and DSP. He enjoys sharing his experience in making complex designs and testbenches easy and fun. He has also contributed to the IEEE P1076-2008 VHDL standard, and continues working towards advancing the microelectronics industry. He has served as a reviewer for several international journals and conferences. Daniel is a Senior Member of the IEEE